The complexity of integrated circuits has dramatically increased during the last decade. System-on-chip and other multiple-core integrated circuits are being developed in order to support various applications such as but not limited to multimedia applications, real time applications and the like.
Modern integrated circuits are capable of executing a large amount of tasks substantially in parallel. Some of these tasks require a transfer of relatively large amounts of data between memory mapped devices. A Multiple-channel Direct Memory Access (DMA) controller can manage multiple data transfers while reducing the load from the integrated circuit cores (processors).
The following patents and patent applications, all being incorporated herein by reference, describe various DMA controllers: U.S. Pat. No. 6,738,881 of Olivier et al, U.S. Pat. No. 6,122,679 of Wunderlich, U.S. Pat. No. 5,450,551 of Amini et al., U.S. Pat. No. 6,728,795 of Farazmandnia et al., U.S. Pat. No. 4,502,117 of Kihara, U.S. Pat. No. 4,556,952 of Brewer et al., U.S. Pat. No. 5,838,993 of Riley at el., U.S. Pat. Nos. 5,692,216, 5,603,050 and 5,884,095 of Wolford et al., U.S. Pat. No. 6,298,396 of Loyer et al., U.S. Pat. No. 6,542,940 of Morrison et al., U.S. Pat. No. 6,041,060 of Leichty et al., U.S. patent applications serial number 2004/0073721A1 of Goff et al, U.S. patent applications serial number 20040037156A1 of Takashi et al., U.S. patent application publication number 2004021618A1 of Cheung, Japanese patent publication number JP07168741A2 of Hedeki et al., Japanese patent publication number JP06187284A2 of Masahiko, Japanese patent application publication number JP2004252533A2 of Yoshihiro, Japanese patent publication number JP0432-4755A2 of Tadayoshi et al., Japanese patent application publication number JP2004013395A2 of Hiroyuki, Japanese patent application publication number JP08249267A2 of Tetsuya, Japanese patent publication number JP02048757A2 of Katsuyuki et al., and PCT patent application publication number WO2005/013084 of Simon et al.
DMA controllers are required to operate at ever growing rates. Data retrieval operations, especially from relatively slow or busy memory units is time consuming. In some cases the same data is required for different DMA channels. Statistically, a DMA controller can performs multiple time-consuming fetch operations of substantially the same data.
There is a need to provide efficient devices and methods for performing efficient direct memory access operations.